In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETS), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs (field-effect transistors) incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
More particularly, referring to the exemplary prior art nonplanar MOS transistor having a FinFET configuration shown in FIG. 1, a FinFET device 10 generally includes two or more parallel silicon fin structures (or simply “fins”) 12. However, it is to be appreciated that the FinFET device may include just one silicon fin structure.
The fins extend between a common source electrode and a common drain electrode (not shown in FIG. 1). A conductive gate structure 16 “wraps around” three sides of both fins, and is separated from the fins by a standard gate insulator layer 18. Fins may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the near surface of the fins adjacent to the gate insulator 18.
The fin structures (and thus FinFET devices) may be formed on a semiconductor substrate. The semiconductor substrate may be a bulk silicon wafer from which the fin structures are formed or may comprise a silicon on insulator (SOI) wafer disposed on a support substrate. The SOI wafer comprises a silicon oxide layer, and a silicon-comprising material layer overlying the silicon oxide layer. The fin structures are formed from the silicon-comprising material layer. Fin structures are typically formed using conventional photolithographic or anisotropic etching processes (e.g., reactive ion etching (RIE) or the like).
Electrical isolation of the fin structures is necessary in order to avoid electromechanical interference (EMI) and/or parasitic leakage paths between the various devices. Isolating fin structures on a bulk silicon wafer is especially problematic as the silicon of the bulk silicon wafer between the fin structures forms a conduction path. Shallow trench isolation (STI) is a technique used to electrically isolate transistors or electrical devices. Typical STI is created early during the semiconductor device fabrication process, before the transistors are formed. A conventional STI process involves creating an isolation trench in the semiconductor substrate through an anisotropic etch process (such as reactive ion etching (RIE)), and depositing one or more dielectric filler materials (such as silicon oxide) using chemical vapor deposition (CVD) processes to fill the isolation trenches. The deposited dielectric material may then be planarized by a Chemical-Mechanical Polishing (CMP) process that removes the excess dielectric and creates a planar STI structure. In FinFET devices, this planarized oxide then needs to be etched back to form a 5 nm to 20 nm uniformly thick oxide isolation between the fin structures and expose the fin vertical sidewalls for further processing. This conventional technique is difficult to control, often resulting in a dielectric layer that varies in thickness. In addition, more dielectric filler material than is needed to provide isolation is required to be deposited in order to permit etch back (planarization).
In addition, the isolation area on the exposed semiconductor substrate between each fin structure (hereinafter “isolation trench”) has a high aspect ratio. Aspect ratio is the ratio of the depth of the opening to its width. The filling of high aspect ratio isolation trenches is difficult. Even state of the art oxide chemical vapor deposition (CVD) processes such as advanced high density plasma (HDP) or ozone based TEOS (tetraethylorthosilicate) processes cannot reliably fill these high aspect ratio isolation trenches. This causes problems in controlling and creating electrical isolation in FinFET devices.
Additionally, bulk silicon wafers lack an etch stop layer upon which etching of the fin can terminate. Without this etch stop layer, variability in the etch depth results in variability in the fin height. As the amount of current conducted by the FinFET device is proportional to the height of the fin, it is important to minimize variability in the fin height.
Accordingly, it is desirable to provide methods for forming isolation between fin structures of FinFET devices. In addition, it is desirable to provide methods for controllable filling of the high aspect ratio isolation trenches between the fin structures, with fewer process steps, with less dielectric filler material, and which result in less fin height variability for bulk FinFETs. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.